The present invention relates to a semiconductor integrated circuit device and a process for fabricating the same and, particularly, to a technique for realizing a high degree of integration and a high degree of reliability of an electrically rewritable nonvolatile semiconductor memory device.
Among electrically rewritable nonvolatile semiconductor memory devices, flash memories are well known in the art as the one capable of bulk erasing. Since the flash memories are excellent in portability as well as impact resistance and capable of electrical bulk erasing, they are rapidly growing in demand in recent years as memory devices to be used for personal digital assistances such as a mobile personal computer and a digital still camera. One of the important factors in expanding the market for the flash memory is a reduction in bit cost by way of a reduction in memory cell region. For example, as is mentioned in “Applied Physics”, Vol. 65, No. 11, pp. 1114-1124, published by The Japan Society of Applied Physics on Nov. 10, 1996 (Literature 1), various memory cell technologies have heretofore been proposed.
Also, Japanese Patent Laid-open No. 2-110981 (Literature 2) discloses a virtual ground memory cell using a three-layer polysilicon gate.
The memory cell disclosed in the above-mentioned patent literature has a semiconductor region formed in a well in a semiconductor substrate and three gates. The three gates namely are a floating gate formed on the well, a control gate formed over the well and the floating gate, and an erase gate formed between the control gate and the floating gate. The gates are formed from polysilicon, and they are separated from one another by an insulating layer. The floating gate and the well are also separated from each other by an insulating layer. The control gates are connected in the row direction to form a word line. Source/drain diffusion layers are formed in the column direction, and they are of the virtual ground type in which one diffusion layer is shared with adjacent memory cells. Thus, a reduction in pitch in the column direction is achieved. The erase gates are aligned in parallel with a channel and the word line in such a manner that the erase gates are placed between adjacent word lines (control gates).
In the patent literature, in the case of writing data in the memory cell, positive voltages which are independent from each other are applied separately to the word line and the drain, and each of the well, the source, and the erase gate is set to 0V. Thus, hot electrons are generated at the channel portion in the vicinity of the drain so that electrons are injected into the floating gate, thereby raising a threshold value of the memory cell. In the case of erasing data, a positive voltage is applied to the erase gate, and each of the word line, the source, the drain, and the well is set to 0 V. Thus, electrons are injected from the floating gate to the erase gate, thereby lowering the threshold value.
Further, a method of controlling the floating gate potential by the word line and controlling a split channel by a third gate which is different from the floating gate and the control gate is discussed in International Electron Device Meeting Technical Digest (1989), pp. 603-606 (Literature 3).
A common object of the above-mentioned memory cells is to ensure adequate capacitance of a capacitor which is defined between the floating gate and the control gate via an interpoly dielectric film. In order to inject electrons into the floating gate, a positive voltage is applied to the control gate to thereby raise the floating gate potential. In this case, a coupling ratio, which is a ratio of the floating gate voltage to the control gate voltage, is increased owing to the adequate capacitance of the capacitor defined between the floating gate and the control gate via the interpoly dielectric film. Therefore, it is possible to perform data-writing by sufficiently raising the floating gate voltage even if the control gate voltage is low. In a cell where the electron ejection to the substrate, the source drain diffusion layer or the erase gate is performed by applying a negative voltage to the control gate, it is possible to sufficiently lower the floating gate voltage with a low negative control gate voltage by increasing the coupling ratio, thereby enabling to perform the electron injection operation.
The following measures have been taken for the above-mentioned memory cells in order to ensure the adequate capacitance of the capacitor defined between the floating gate and the control gate via the interpoly dielectric film: (1) increasing a surface area of the floating gate by making the floating gate tridimensional so that the adequate capacitance is ensured; and (2) preventing a reduction in capacitance which is caused due to a misalignment of the floating gate with the control gate by forming the control gate, the interpoly dielectric film, and the floating gate in a batch manner.
Since a width of the word line has been narrowed due to the microfabrication of the flash memory, these conventional methods are now in conflict with each other. More specifically, due to the tridimensional floating gate, height differences among the control gate, the interpoly dielectric film, and the floating gate become prominent to make it difficult to perform the batch forming. Therefore, an etch residue on the floating gate causes defects such as a short between memory cells. Further each of the memory cells obtained by the batch forming has a forward tapered shape, which reduces a ratio of capacitance of the interpoly dielectric film to capacitance of the gate insulating layer which is at a portion corresponding to the bottom of the tapered shape.
Further, as the word line width is reduced, a length of a bird's beak which is caused by light oxidation performed for the purpose of compensating for the damage caused by the batch forming on a gate oxidation film is increased to an unignorable degree as compared with the word line width, which adversely effects on a data erase characteristic and reliability of the memory cell.